Mosfets including crystalline sacrificial structures

ABSTRACT

A sub-micron channel length MOSFET includes a seamless epitaxial channel region in a substrate of the MOSFET and a buried device isolation layer beneath the seamless epitaxial channel region. In some embodiments according to the invention, a buried device isolation layer includes the buried device isolation layer beneath a central portion of the seamless epitaxial channel and absent from sidewalls of source/drain regions of the MOSFET.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. patent application Ser. No.11/050,557, filed Feb. 3, 2005, and claims priority to Korean PatentApplication No. 2004-08052 filed on Feb. 6, 2004 in the KoreanIntellectual Property Office (KIPO), the entire contents of which arehereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and specificallyto Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETS).

BACKGROUND

As semiconductor devices have become more highly integrated, a channellength (i.e., the distance between a source region and a drain region ofthe MOS field effect transistor) may be reduced. The reduction of thechannel length may cause short channel effects. Methods of formingsource/drain regions including an LDD (lightly doped drain) structurehave been proposed in order to reduce/prevent short channel effects.However, these methods may not be as effective when a line width of agate electrode is less than 0.1 μm. Korean Laid-Open patent No.2000-041698, Japanese patent No. H9-045904, Korea Laid-Open patent No.2000-056248, discuss techniques for forming a buried insulation regionunder the channel region to suppress short channel effects.

FIG. 1 is a perspective view and FIG. 2 is a cross-sectional viewillustrating a conventional MOSFET including a buried insulation region.Referring to FIG. 1, insulation patterns 20 are formed on apredetermined region of the semiconductor substrate 10. The insulationpatterns 20 are formed in a region of the substrate that will be under agate of the MOSFET, to help reduce a short channel effects.

An epitaxial layer 30 is formed on the semiconductor substrate 10 usingepitaxial growth. The epitaxial layer 30 is formed to have a thicknessthicker than that of the insulation pattern 20. Therefore, as shown inthe drawing, the epitaxial layer 30 is also formed on the insulationpattern 20. After the epitaxial layer 30 and the semiconductor substrate10 are sequentially patterned to form a trench to define an activeregion, a device isolation pattern 40 is formed in the trench.

The insulating pattern 20 is formed of an amorphous material, such asoxide and nitride, which causes the epitaxial layer 30 to be grown inseparate portions (or individually) from the underlying substrate 10around the insulating pattern 20. The separate portions of the epitaxiallayer 30 meet above the insulating pattern 20 to form a discontinuousboundary 35 (or seam) in the epitaxial layer 30 in a region that is tobe the channel region of the MOSFET.

Referring to FIG. 2, a gate insulation layer 50 and a gate pattern 60are formed sequentially on the epitaxial layer 30. Source/drain regions70 are formed in the epitaxial layer 30 on both sides of the gatepattern 60. The portion of the epitaxial layer 30 including the seamunder the gate pattern 60 (i.e., between the source/drain regions) isused as the channel region of the MOSFET. The discontinuous boundary 35in the epitaxial layer 30 may adversely affect the electricalcharacteristics of the MOSFET. In view of the above, the conventionaltechniques discussed above using the insulation pattern 20 may suppressshort channel effects, but may also degrade electrical characteristicsof the MOSFET.

SUMMARY

In some embodiments according to the invention, a sub-micron channellength MOSFET includes a seamless epitaxial channel region in asubstrate of the MOSFET and a buried device isolation layer beneath theseamless epitaxial channel region. In some embodiments according to theinvention, a buried device isolation layer includes the buried deviceisolation layer beneath a central portion of the seamless epitaxialchannel and absent from sidewalls of source/drain regions of the MOSFET.

In some embodiments according to the invention, a buried deviceisolation layer includes the buried device isolation layer beneath aside portion of the seamless epitaxial channel including on sidewalls ofsource/drain regions of the MOSFET. In some embodiments according to theinvention, a buried device isolation layer includes the buried deviceisolation layer beneath an entire length of the seamless epitaxialchannel and including on sidewalls of source/drain regions of theMOSFET.

In some embodiments according to the invention, an upper surface of theburied device isolation layer is buried beneath a surface of theseamless epitaxial channel by an amount sufficient to avoid a floatingbody effect. In some embodiments according to the invention, a linerlayer surrounding the device isolation layer includes a silicon nitridelayer, a silicon oxynitride layer, and/or a silicon oxide layer. In someembodiments according to the invention, a thermal oxidation layersurrounds the liner layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view for explaining a method of fabricating aMOS field effect transistor in accordance with a prior art.

FIG. 2 is a cross-sectional view for explaining a method of fabricatinga MOS field effect transistor in accordance with a prior art.

FIG. 3 is a top plane view of a MOS field effect transistor inaccordance with one exemplary embodiment of the present invention.

FIGS. 4A through 9A are cross-sectional views taken along a dotted lineI-I in FIG. 3.

FIGS. 4B through 9B are cross-sectional views taken along a dotted lineII-II in FIG. 3.

FIG. 10 is a cross-sectional view of a MOS field effect transistor inaccordance with another exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view of a MOS field effect transistor inaccordance with still another exemplary embodiment of the presentinvention.

FIG. 12 is a perspective view of a MOS field effect transistor inaccordance with one exemplary embodiment of the present invention.

DESCRIPTION EMBODIMENTS ACCORDING TO THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. Like numbers refer to like elements throughout.As used herein the term “and/or” includes any and all combinations ofone or more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers refer to like elementsthroughout the specification.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in the Figures is turned over, elements describedas being on the “lower” side of other elements would then be oriented on“upper” sides of the other elements. The exemplary term “lower”, cantherefore, encompasses both an orientation of “lower” and “upper,”depending of the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The exemplary terms “below” or “beneath” can, therefore,encompass both an orientation of above and below.

Embodiments of the present invention are described herein with referenceto cross-section (and/or plan view) illustrations that are schematicillustrations of idealized embodiments of the present invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the present invention should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, an etched region illustrated ordescribed as a rectangle will, typically, have rounded or curvedfeatures. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the precise shapeof a region of a device and are not intended to limit the scope of thepresent invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein. It will also be appreciated by those ofskill in the art that references to a structure or feature that isdisposed “adjacent” another feature may have portions that overlap orunderlie the adjacent feature.

As disclosed herein in further detail, in some embodiments according tothe invention, an epitaxial semiconductor layer is grown on an uppersurface of a sacrificial crystalline structure and on a substrate toform a buried sacrificial structure. The buried sacrificial structure isremoved to form a void in place of the buried sacrificial structure anda device isolation layer is formed in the void. Forming the buriedsacrificial structure of a crystalline material may promote theformation of the epitaxial semiconductor layer from the sacrificialcrystalline structure, which may help avoid the formation of a seam inthe epitaxial layer above the buried sacrificial structure in a portionof the substrate which provides the channel region of the MOSFET.Avoiding the formation of the seam, may promote the growth of theepitaxial semiconductor layer in the channel having better electricalproperties, particularly in devices sized so that short channel effectsmay be an issue.

FIG. 3 is a top plane view of a MOS field effect transistor inaccordance with some embodiments of the present invention, FIGS. 4Athrough 9A are cross-sectional views taken along a dotted line I-I inFIG. 3, and FIGS. 4B through 9B are cross-sectional views taken along adotted line II-II in FIG. 3.

Referring to FIGS. 3, 4A through 4B, a first mask layer is formed on asemiconductor substrate 100. In this case, the semiconductor substrate100 is formed of a semiconductor having a crystalline structure (e.g., apolysilicon structure), and the first mask layer may be formed of asilicon oxide layer and a silicon nitride layer that are sequentiallystacked. However, other kinds of materials may be used as the firstsemiconductor substrate 100 and the first mask layer.

The first mask layer is patterned to form a first mask pattern 110having an opening 115 exposing a predetermined region of thesemiconductor substrate 100. Using the first mask pattern 110 as an etchmask, the exposed semiconductor substrate 100 is etched to form a firsttrench or recess 201 (i.e., a buried insulation region) having a firstdepth d₁. In some embodiments according to the invention, the firsttrench 201 has a line width smaller than that of a gate pattern (ofwhich line width is smallest in a semiconductor device). Therefore, theopening 115 of the first mask pattern 110, which defines the firsttrench 201, should be formed to also have a micro width. The first maskpattern 110 may be formed using any etch/lithography process, aphotoresist reflow process, a spacer masking process, and/or a chemicaladhesion process.

A sacrificial pattern (or sacrificial crystalline structure) 120 isformed to fill the first trench 210. According to the present invention,the sacrificial pattern 120 has a crystalline structure and formed of amaterial having etch selectivity with respect to the semiconductorsubstrate 100. That is, the sacrificial pattern 120 is formed of amaterial having etch rate faster than that of the semiconductorsubstrate 100 in a specific etch recipe in order to reduce etch of thesemiconductor substrate 100. According to some embodiments of thepresent invention, the sacrificial pattern 120 may be a silicongermanium pattern formed by epitaxial growth. During formation of thesacrificial pattern 120, the first mask pattern 110 is used as anepitaxial prevent mask (or mask to prevent epitaxial growth from theportion of the substrate 100 which is covered by the mask). That is, thefirst mask pattern 110 covers a top surface of the semiconductorsubstrate 100 except for the first trench 201 so as to form thesacrificial pattern 120 only inside the first trench 201.

Referring to FIGS. 3, 5A through 5B, the first mask pattern 110 isremoved. Therefore, upper surfaces of the semiconductor substrate 100and the sacrificial pattern 120 are exposed. An epitaxial semiconductorlayer 130 is formed on the exposed semiconductor substrate 100 and thesacrificial pattern 120 to provide the sacrificial pattern 120 as aburied sacrificial structure. In some embodiments according to theinvention, the epitaxial semiconductor layer 130 is formed of asemiconductor having a crystalline structure and may be formed ofpolysilicon identical to the semiconductor substrate 100.

As fully described above, the sacrificial pattern 120 may be formed ofsemiconductor material having a crystalline structure. Therefore, theepitaxial semiconductor layer 130 may be grown from the upper surface ofthe buried sacrificial structure as well as from the adjacent uppersurface of the substrate 100 to provide a seamless single crystallinestructure (without a discontinuous boundary) in the epitaxialsemiconductor layer 130. As a result, the epitaxial semiconductor layer130 may be used as a channel region of the MOSFET. In some embodimentsaccording to the invention, a thickness of the epitaxial semiconductorlayer 130 may be determined considering a thickness of the channelregion, a depth of the source/drain regions, recess of a subsequentprocess, etc.

Referring to FIGS. 3, 6A through 6B, a second mask pattern 140 is formedon the epitaxial semiconductor layer 130 to cross over the sacrificialpattern 120. Using the second mask pattern 140 as an etch mask, theepitaxial semiconductor layer 130 and the semiconductor substrate 100are successively etched. Therefore, a second trench (or recess) 202 isformed around the second mask pattern 140 to define an active region.

Considering a planar arrangement of the second mask pattern 140 and thesacrificial pattern 120, the sacrificial pattern 120 is disposed under acentral portion of the second mask pattern 140, and both edges thereofare exposed at each side of the second mask pattern 140 (with referenceto FIG. 3). Thus, the sacrificial pattern 120 is disposed in a centralportion of the active region, and both edges thereof are exposed by thesecond trench 202 (with reference to FIG. 6B).

The second mask pattern 140 may be formed of a silicon oxide layer, asilicon nitride layer, and/or a silicon oxynitride layer. In someembodiments according to the invention, the second trench 202 may beformed using an anisotropic etch having etch selectivity with respect tothe second mask pattern 140.

Referring to FIGS. 2, 7A through 7B, the exposed sacrificial pattern 120is removed by using an etchant recipe with a selectivity with respect tothe semiconductor substrate 100 and the epitaxial semiconductor layer130. In some embodiments according to the invention, the sacrificialpattern 120 is removed using an isotropic etch and preferably an etchrecipe capable of etching silicon germanium faster than silicon.Therefore, both inner sidewalls of the second trench 202 and the firsttrench 201 are exposed (with reference to FIG. 7B). Furthermore, removalof the exposed sacrificial pattern 120 forms a void in the substrate inplace of the exposed sacrificial pattern 120 in the first trench 201.

A liner 150 may be formed on an entire surface of the semiconductorsubstrate that surrounds the sacrificial pattern 120. The liner 150conformally covers the inner sidewalls of the first and second trenches201 and 202 and the exposed surface of the second mask pattern 140. Insome embodiments according to the invention, the liner 150 is a siliconnitride layer, a silicon oxynitride layer, and/or a silicon oxide layer.In some embodiments according to the invention, before forming the liner150, a thermal oxidation process may be performed to form a thermaloxide layer (not shown) on the inner sidewalls of the first and secondtrenches 201 and 202. The thermal oxide layer may repair etch damageoccurring during the formation of the first and second trenches 210 and202. The liner 150 may reduce/prevent pollutants from penetrating intothe active region, especially into the epitaxial semiconductor layer130.

Referring to FIGS. 3, 8A through 8B, a device isolation layer is formedon the liner 150. The device isolation layer is formed of a siliconoxide layer, and may be formed of MTO and HDP oxide layers that aresequentially stacked. Other materials may also be used to form thedevice isolation layer.

In some embodiments according to the invention, the device isolationlayer is formed to fill the first and second trenches 201 and 202. Insome embodiments according to the invention, the first trench 201 is notfilled with the device isolation layer, where the trench 201 is under alow pressure, nearly a vacuum, or filled with gases such as nitrogen orhelium.

The device isolation layer is etched to form a device isolation pattern160 filling the second trench 202. The formation of the device isolationpattern 160 includes planarizingly etching the second isolation layeruntil the second mask pattern 140 is exposed. The planarizing may becarried out using a chemical-mechanical polishing (CMP).

The exposed second mask pattern 140 is removed to expose a top surfaceof the epitaxial semiconductor layer 130. A gate insulating layer 170 isformed on a top surface of the exposed epitaxial semiconductor layer130. The second mask pattern 140 can be removed using an etch recipecapable of etching the silicon nitride layer selectively, minimizingetching of the silicon and silicon oxide layer. In some embodimentsaccording to the invention, the etch recipe is an isotropic wet etchusing phosphoric acid. In some embodiments according to the invention,the gate insulating layer 170 is a silicon oxide layer formed through athermal oxidation process.

Referring to FIGS. 3, and 9A through 9B, a gate pattern 180 is formed onthe gate insulating layer 170 to cross over the active region and thefirst trench 201. A low concentration ion implantation process isperformed using the gate pattern 180 as a mask to form lightly dopedregions 190 in the active region at both sides of the gate pattern 180.Gate spacers 185 are formed on a sidewall(s) of the gate pattern 180. Ahigh concentration ion implantation is performed using the gate pattern180 and the gate spacer 185 as a mask to form heavily doped regions 195in the active region on both sides of the gate spacer 185.

The heavily doped region 195 and the lightly doped region 190 aredisposed overlap each other and form a lightly doped drain (LDD) regionin the substrate 100. The LDD regions formed at both sides of the gatepattern 180 serve as source/drain regions of the MOSFET.

FIGS. 10 and 11 are cross-sectional views illustrating MOSFETS formedaccording to some embodiments of the invention. It will be understoodthat the embodiments according to the invention illustrated by FIGS. 10and 11 include structures which are analogous to those disclosed abovein reference to FIGS. 3-9B.

Referring to FIG. 10, the first trench 201′ is formed to insulate thechannel region and the semiconductor substrate 100 electrically. Thatis, edges of the first trench (or recess) 201′ are formed to lateralsurfaces of the source region and the drain region. In other words, thefirst trench 201′ extends beneath a central portion of the channelregion and extends into the source/drain regions at opposing ends of thechannel. As a result, the first trench 201′ has a line width that is thesame as or larger than that of the gate pattern 180. Therefore, thefirst mask pattern 110 may be formed easily because the opening 115 inFIGS. 4A and 4B may not be required.

In addition, according to some embodiments of the invention, a surfacearea of the sacrificial pattern 120 exposed by the second trench 202becomes wide, such that the step of removing the sacrificial pattern 120in FIGS. 7A and 7B may be easily performed. After the sacrificialpattern 120 is removed, the first trench 201′ may be filled with thedevice isolation pattern 160.

In some embodiments according to the invention, the channel region issurrounded by the source/drain regions and the second trench 202.Moreover, a thickness of the channel region may be controlled using theepitaxial growth technology so that the channel region is depletedsufficiently and minority charges are not collected on a lower portionof the channel region. As a result, the floating body effect can bereduced/prevented in contrast to an SOI wafer arrangement. Furthermore,the source/drain regions extend into both the epitaxial semiconductorlayer 130 and into the underlying semiconductor substrate 100 (so thatthe source/drain regions may be formed relatively deep compared to anSOI arrangement) to prevent/reduce an unacceptable increase inresistance.

Referring to FIG. 11, the first trenches 201 a and 201 b may be formedin one cell so as to prevent the floating body effect. In other words,the two first trenches 201 a and 201 b can be formed on the region wherethe gate pattern 180 cross over the active region. One of the firsttrenches 201 a is formed to adjoin a lateral surface of the sourceregion and the other of the first trenches 201 b is formed to adjoin alateral surface of the drain region. Moreover, the first trench 201 isnot formed beneath a central portion of the channel.

The channel region is electrically connected to the substrate biasthrough the semiconductor substrate 100 beneath the central portion ofthe channel between the trenches 201 a and 201 b. As a result, thefloating body effect can be prevented/reduced.

In the exemplary embodiments in FIGS. 10 and 11, a contact area of a PNjunction of the source/drain regions and the semiconductor substrate 100may be reduced. Therefore, a leakage current at the PN junction can bereduced in some embodiments according to the invention.

FIG. 12 is a schematic cross-sectional view of a MOS field effecttransistor in accordance with some embodiments of the invention. FIGS.9A and 9B are cross-sectional views of a MOSFET corresponding toembodiments illustrated by FIG. 12. Referring to FIGS. 9A, 9B, and 12, adevice isolation pattern 160 is disposed in a predetermined region of asemiconductor substrate 100 having a crystalline structure. An epitaxialsemiconductor layer 130 is disposed on the semiconductor substrate 100surrounded by the device isolation pattern 160. As a result, the deviceisolation pattern 160 surrounds the epitaxial semiconductor layer 130and the semiconductor substrate 100 under the same. The regionsurrounded by the device isolation pattern 160 is defined as an activeregion.

The epitaxial semiconductor layer 130 may be formed of semiconductorhaving a crystalline structure such as the material of the semiconductorsubstrate 100. In some embodiments according to the invention, thesemiconductor substrate 100 and the epitaxial semiconductor layer 130are polysilicon. Moreover, the epitaxial semiconductor layer 130comprises a “seamless” epitaxial channel region beneath the gateelectrode in a central region of the channel. It will be understood thatthe term “seamless” includes epitaxial channel regions having acrystalline structure that is grown on an underlying crystallinesacrificial structure. Therefore, the epitaxial semiconductor layer 130may be used as a channel of the transistor. In addition, the epitaxialsemiconductor layer 130 is epitaxially grown from the semiconductorsubstrate 100, such that the two layers form a continuous singlecrystalline structure silicon.

A buried insulation region 201 is disposed under the epitaxialsemiconductor layer 130. The buried insulation region 201 penetrates thesemiconductor substrate 100 constituting the active region in parallelto be connected to the device isolation pattern 160. The buriedinsulation region 201 may be filled with the material of the deviceisolation pattern 160, under a low pressure of nearly vacuum, or filledwith nitrogen or helium gases. A liner 150 or a thermal oxide layer maybe interposed between the device isolation pattern 160 and thesemiconductor substrate 100 and between the device isolation pattern 160and the epitaxial semiconductor layer 130. The liner 150 and the thermaloxide layer may be formed on inner sidewalls of the buried insulationregions 201.

A gate pattern 180 crossing over the active region is disposed on thedevice isolation patter 160. Preferably, the gate pattern 180 isdisposed on the buried insulation region 201. The epitaxialsemiconductor layer 130 is interposed between the gate pattern 180 andthe buried insulation region 201. Moreover a gate insulation layer 170is disposed between the gate pattern and the epitaxial semiconductorlayer 130.

Source regions 190 and 195 and drain regions 190 and 195 are disposed inthe active region at both sides of the gate pattern 180. The channelregion and the buried insulation region 201 are interposed between thesource regions 190 and 195 and the drain regions 190 and 195. Therefore,the short channel effect can be decreased by the buried insulationregion 201 that insulates the source region and the drain regionelectrically.

In still another exemplary embodiment of the present invention, theburied insulation region 201 may be disposed to adjoin lateral sidewallsof the source and drain regions. The electrical resistance of thesource/drain regions can be reduced as illustrated in FIGS. 10 and 11,and the leakage current of the PN junction may be decreased. Two buriedinsulation region 201 may be disposed in each one cell and the abovefloating body effect can be minimized.

According to some embodiments of the present invention, an epitaxialsemiconductor layer is formed on a sacrificial pattern and asemiconductor substrate that have a crystalline structure via epitaxialgrowth. Therefore, the epitaxial semiconductor layer used as a channelregion is formed to have a crystalline structure without a discontinuousboundary surface (i.e., seamless).

In some embodiments according to the invention, a gate pattern of thepresent invention is disposed on a first trench or a buried insulationregion where the sacrificial pattern is replaced. As a result, theburied insulation region is disposed between the source and drainregions as an insulation structural material.

In some embodiments according to the invention, the buried insulationregion may be formed to contact lateral surfaces of the source and drainregions. An area where the source/drain regions contact the substrate isdecreased, such that the leakage current generated at the source/drainregions can be reduced.

Since the source/drain regions may be formed deep, the source/drain mayhave sufficiently low resistance and the MOSFET can be fabricated tosuppress disadvantages (e.g., floating body effect) but maintainadvantages of the SOI substrate even if a structure and a disposition ofthe buried insulation region are varied.

Many alterations and modifications may be made by those having ordinaryskill in the art, given the benefit of the present disclosure, withoutdeparting from the spirit and scope of the invention. Therefore, it mustbe understood that the illustrated embodiments have been set forth onlyfor the purposes of example, and that it should not be taken as limitingthe invention as defined by the following claims. The following claimsare, therefore, to be read to include not only the combination ofelements which are literally set forth but all equivalent elements forperforming substantially the same function in substantially the same wayto obtain substantially the same result. The claims are thus to beunderstood to include what is specifically illustrated and describedabove, what is conceptually equivalent, and also what incorporates theessential idea of the invention.

1. A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)comprising: a seamless epitaxial channel region in a substrate of asub-micron channel length MOSFET; and a buried device isolation layerbeneath the seamless epitaxial channel region.
 2. A MOSFET according toclaim 1 wherein a buried device isolation layer comprises the burieddevice isolation layer beneath a central portion of the seamlessepitaxial channel and absent from sidewalls of source/drain regions ofthe MOSFET.
 3. A MOSFET according to claim 1 wherein a buried deviceisolation layer comprises the buried device isolation layer beneath aside portion of the seamless epitaxial channel including on sidewalls ofsource/drain regions of the MOSFET.
 4. A MOSFET according to claim 1wherein a buried device isolation layer comprises the buried deviceisolation layer beneath an entire length of the seamless epitaxialchannel and including on sidewalls of source/drain regions of theMOSFET.
 5. A MOSFET according to claim 1 wherein an upper surface of theburied device isolation layer is buried beneath a surface of theseamless epitaxial channel by an amount sufficient to avoid a floatingbody effect.
 6. A MOSFET according to claim 1 further comprising: aliner layer surrounding the device isolation layer comprising a siliconnitride layer, a silicon oxynitride layer, and/or a silicon oxide layer.7. A MOSFET according to claim 6 further comprising: a thermal oxidationlayer surrounding the liner layer.